HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1059
HD6417320
Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417320.pdf
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Bit
5
4
Bit Name
ORER
ERS
Initial
Value
0
0
R/W
R/W
R/W
Description
Overrun Error
Indicates that an overrun error occurred during reception,
resulting in abnormal termination.
0: Indicates that reception is in progress, or that reception
[Clearing conditions]
•
•
1: Indicates that an overrun error occurred during reception*
[Setting condition]
When the RDRF bit is set to 1 and the next serial reception
is completed.
Notes:
Error Signal Status
Indicates the status of error signals returned from the receive
side during transmission. In T = 1 mode, this flag is not set.
0: Indicates that an error signal indicating detection of a
[Clearing conditions]
•
•
1: Indicates that an error signal indicating detection of a
[Setting condition]
When an error signal is sampled.
Note:
parity error was not sent from the receive side
parity error was sent from the receive side
was completed normally*
On reset
When 0 is written to the ORER bit
On reset
When 0 is written to the ERS bit
Even if the TE bit in SCSCR is cleared to 0, the
ERS flag is unaffected, and the previous state is
retained.
1. When the RE bit in SCSCR is cleared to 0, the
2. In SCRDR, the received data before the overrun
ORER flag is unaffected and the previous state is
retained.
error occurred is lost, and the data that had been
received at the time when the overrun error
occurred is retained. Further, with the ORER bit
set to 1, subsequent serial reception cannot be
continued.
Rev. 3.00 Jan. 18, 2008 Page 997 of 1458
1
Section 30
SIM Card Module (SIM)
REJ09B0033-0300
2
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