HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 723

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

[Legend]
S:
SLA:
R/W:
A:
DATA: Transfer data
P:
20.4.2
In master transmit mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. For master transmit mode operation timing, refer to
figures 20.5 and 20.6. The transmission procedure and operations in master transmit mode are
described below.
1. Set the ICE bit in ICCR1 to 1. Set the MLS bit in ICMR and the CKS4 to CKS0 bits in ICCKS
2. Read the BBSY flag in ICCR2 to confirm that the bus is free. Set the MST and TRS bits in
3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte data
4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1
to 1. (Initial setting)
ICCR1 to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using MOV
instruction. (Start condition issued) This generates the start condition.
show the slave address and R/W) to ICDRT. At this time, TDRE is automatically cleared to 0,
and data is transferred from ICDRT to ICDRS. TDRE is set again.
at the rise of the 9th transmit clock pulse. Read the ACKBR bit in ICIER, and confirm that the
slave device has been selected. Then, write second byte data to ICDRT. When ACKBR is 1,
the slave device has not been acknowledged, so issue the stop condition. To issue the stop
condition, write 0 to BBSY and SCP using MOV instruction. SCL is fixed low until the
transmit data is prepared or the stop condition is issued.
Start condition. The master device drives SDA from high to low while SCL is high.
Slave address
Indicates the direction of data transfer: from the slave device to the master device when
R/W is 1, or from the master device to the slave device when R/W is 0.
Acknowledge. The receive device drives SDA to low.
Stop condition. The master device drives SDA from low to high while SCL is high.
SDA
SCL
Master Transmit Operation
S
SLA
1-7
R/W
8
Figure 20.4
9
A
1-7
DATA
I
2
C Bus Timing
8
9
A
Rev. 3.00 Jan. 18, 2008 Page 661 of 1458
1-7
Section 20
DATA
8
I
9
A
2
C Bus Interface (IIC)
REJ09B0033-0300
P