HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 282

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 Exception Handling
7.1.4
INTEVT2 is assigned to address H'A4000000 and consists of a 12-bit exception code. Exception
codes to be specified in INTEVT2 are those for interrupt requests. These exception codes are
automatically specified by the hardware when an exception occurs. INTEVT2 cannot be modified
using the software.
7.1.5
TEA is assigned to address H'FFFFFFFC and the virtual address for an exception occurrence is
stored in this register when an exception related to memory accesses occurs. TEA can be modified
using the software.
Rev. 3.00 Jan. 18, 2008 Page 220 of 1458
REJ09B0033-0300
Bit
31 to 12
11 to 0
Bit
31 to 0
Interrupt Event Register 2 (INTEVT2)
Exception Address Register (TEA)
Bit Name

INTEVT2
Bit Name
TEA
Initial
Value
All 0

Initial
Value
All 0
R/W
R
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
12-bit Exception Code
Description
The virtual address for an exception occurrence