HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 356

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9
9.4.2
This register specifies the type of memory connected to each space, data-bus width of each space,
and the number of wait cycles between access cycles.
Do not access external memory other than area 0 until the CSnBCR initialization is completed.
(n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
Rev. 3.00 Jan. 18, 2008 Page 294 of 1458
REJ09B0033-0300
Bit
31
30
29
28
Bit Name

IWW2
IWW1
IWW0
CSn Space Bus Control Register (CSnBCR)
Bus State Controller (BSC)
Initial
Value
0
0
1
1
R/W
R
R/W
R/W
R/W
Description
Reserved
This bit is always read as 0. The write value should always
be 0.
Idle Cycles between Write-Read Cycles and Write-Write
Cycles
These bits specify the number of idle cycles to be inserted
after the access to a memory that is connected to the space.
The target access cycles are the write-read cycle and write-
write cycle.
000: No idle cycle
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted