HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 278

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 X/Y Memory
6.3.3
When the X/Y memory is accessed via the I bus using the cache from the CPU and DSP, correct
operation cannot be guaranteed. If the X/Y memory is accessed while the cache is enabled
(CCR1.CE = 1), it is advisable to access the X/Y memory via the L bus from space P2 or Uxy. If
the X/Y memory is accessed from space P0, P3, or U0, it is advisable to access the X/Y memory
via the I bus, which does not use the cache, with MMU setting enabled (MMUCR.AT = 1) and
cache disabled (C bit = 0) as page attributes. Since access using the MMU occurs via the I bus,
several cycles are necessary (the number of necessary cycles varies according to the ratio between
the internal clock (Iφ) and bus clock (Bφ) or the operation state of the DMAC). In a program that
requires high performance, it is advisable to access the X/Y memory from space P2 or Uxy. The
relationship described above is summarized in table 6.2.
Table 6.2
Note:
6.3.4
In sleep mode, I bus master modules such as the DMAC cannot access the X/Y memory.
Rev. 3.00 Jan. 18, 2008 Page 216 of 1458
REJ09B0033-0300
CCR1.CE
0
0
1
1
A: Accessible (recommended)
B: Accessible
C: Accessible (Note that MMU page attribute must be specified as cache disabled by
X: Not accessible
MMU and Cache Settings
Sleep Mode
clearing the C bit to 0.)
Setting
MMU and Cache Settings
MMUCR.AT
0
1
0
1
P0, U0
B
B
X
C
Virtual Address Space and Access Enabled or Disabled
P1
B
B
X
X
P2, Uxy
A
A
A
A
P3
B
B
X
C