HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 163

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(1) Double data transfer instructions (MOVX.W, MOVY.W)
With double data transfer instructions, X memory and Y memory can be accessed in parallel.
In this case, the specific buses called X bus and Y bus are used to access X memory and Y
memory, respectively. To fetch the CPU instructions, the L bus is used. Accordingly, no conflict
occurs among X, Y, and L buses.
Load instructions for X memory specify the X0 or X1 register as the destination operand. Load
instructions for Y memory specify the Y0 or Y1 register as the destination operand. Store registers
for X or Y memory specify the A0 or A1 register as the source operand. These instructions use
only word data (16 bits). When a word data transfer instruction is executed, the upper word of
register operand is used. To load word data, data is loaded to the upper word of the destination
register and the lower word of the destination register is automatically cleared to 0.
Legend
XAB
XDB
YAB
YDB
LAB
LDB
CDB
: X bus (address)
: X bus (data)
: Y bus (address)
: Y bus (data)
: L bus (address)
: L bus (data)
: C bus (data)
X memory
Y memory
XAB
[15:0]
Figure 3.4 DSP Registers and Bus Connections
YAB
[15:0]
XDB
[15:0]
YDB
[15:0]
CPU
DSP unit
CDB
[31:0]
Rev. 3.00 Jan. 18, 2008 Page 101 of 1458
DSR
A0
A1
M0
M1
X0
X1
Y0
Y1
Section 3 DSP Operating Unit
A0G
A1G
LAB
[31:0]
REJ09B0033-0300
LDB
[31:0]