HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 737

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

20.5
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full,
NACK receive, STOP recognition, and arbitration lost/overrun error. Table 20.3 shows the
contents of each interrupt request.
Table 20.3 Interrupt Requests
When interrupt conditions described in table 20.3 are 1 and the I bit in CCR is 0, the CPU
executes an interrupt exception processing. Interrupt sources should be cleared in the exception
processing. TDRE and TEND are automatically cleared to 0 by writing the transmit data to
ICDRT. RDRF are automatically cleared to 0 by reading ICDRR. TDRE is set to 1 again at the
same time when transmit data is written to ICDRT. When TDRE is cleared to 0, then an excessive
data of one byte may be transmitted.
Interrupt Request
Transmit Data Empty
Transmit End
Receive Data Full
STOP Recognition
NACK Receive
Arbitration Lost/Overrun Error
Interrupt Request
Abbreviation
TXI
TEI
RXI
STPI
NAKI
Interrupt Condition
(TEND=1)
(TDRE=1)
(RDRF=1)
(STOP=1)
{(NACKF=1)+(AL=1)}
Rev. 3.00 Jan. 18, 2008 Page 675 of 1458
Section 20
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(STIE=1)
(TIE=1)
(TEIE=1)
(RIE=1)
I
2
C Bus Interface (IIC)
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(NAKIE=1)
REJ09B0033-0300