HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 892

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 25
25.3.36 Control Register 0 (CTLR0)
CTLR0 sets functions of ASCE, PWMD, RSME, and RWUP.
Rev. 3.00 Jan. 18, 2008 Page 830 of 1458
REJ09B0033-0300
Bit
7 to 5
4
3
2
1
0
Bit
name
c
RWUPS
RSME

ASCE

USB Function Controller (USBF)
Initial
value
All 0
0
0
0
0
0
R
R/W
R
R/W
R
R/W
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Remote Wakeup Status
Status bit to indicate that the remote wakeup from the
host is enabled/disabled. Indicates 0 when the remote
wakeup is disabled with Device Remote Wakeup by the
Set Feature/Clear Feature request and indicates 1 when
it is enabled.
Resume Enable
Bit to clear the suspend state (performs the remote
wakeup)
When this bit is written to 1, a resume register is set.
When this bit will be used, be sure to hold to 1 for one
clock or more at 12 MHz in minimum and then clear to 0
again.
Reserved
This bit is always read as 0. The write value should
always be 0.
Automatic Stall Clear Enable
When this bit is set to 1, the stall handshake is returned
to the host and the stall setting bit (EPSTLR/EPXSTL) of
the returned endpoint is automatically cleared. Control in
a unit of endpoint is disabled as this bit is common for all
endpoints. When this bit is set to 0, be sure to clear the
stall setting bit of each endpoint by using software.
This bit should be set to 1 before each stall bit in EPSTL
is set to 1.
Reserved
This bit is always read as 0. The write value should
always be 0.
Description