HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1184

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 33 User Break Controller (UBC)
Rev. 3.00 Jan. 18, 2008 Page 1122 of 1458
REJ09B0033-0300
Bit
13
12
11
10
9, 8
7
Bit Name
SCMFDA
SCMFDB
PCTE
PCBA

DBEB
Initial
Value
0
0
0
All 0
0
0
R/W
R/W
R/W
R/W
R
R/W
R/W
Description
I Bus Cycle Condition Match Flag A
When the I bus cycle condition in the break conditions
set for channel A is satisfied, this flag is set to 1 (not
cleared to 0). In order to clear this flag, write 0 into this
bit.
0: The I bus cycle condition for channel A does not
1: The I bus cycle condition for channel A matches
I Bus Cycle Condition Match Flag B
When the I bus cycle condition in the break conditions
set for channel B is satisfied, this flag is set to 1. In
order to clear this flag, write 0 into this bit.
0: The I bus cycle condition for channel B does not
1: The I bus cycle condition for channel B matches
PC Trace Enable
0: Disables PC trace
1: Enables PC trace
PC Break Select A
Selects the break timing of the instruction fetch cycle
for channel A as before or after instruction execution.
0: PC break of channel A is set before instruction
1: PC break of channel A is set after instruction
Reserved
These bits are always read as 0. The write value
should always be 0.
Data Break Enable B
Selects whether or not the data bus condition is
included in the break condition of channel B.
0: No data bus condition is included in the condition of
1: The data bus condition is included in the condition
execution
execution
channel B
of channel B
match
match