HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 884

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 25
25.3.19 EP1 Data Register (EPDR1)
EPDR1 is a 128-byte receive FIFO buffer for endpoint 1. EPDR1 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. The number of receive byte is displayed in
the EP1 receive data size register. The buffer on read side can be received again by writing
EP1RDFN in the trigger register to 1 after data is read. The receive data of this FIFO buffer can be
transferred by DMA. This FIFO buffer can be initialized by means of EP1CLR in the FCLR0
register.
25.3.20 EP2 Data Register (EPDR2)
EPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. EPDR2 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO
buffer and EP2PKTE in the trigger register is set, one packet of transmit data is fixed, and the
dual-FIFO buffer is switched over. Transmit data for this FIFO buffer can be transferred by DMA.
This FIFO buffer can be initialized by means of EP2CLR in the FCLR0 register.
25.3.21 EP3 Data Register (EPDR3)
EPDR3 is an 8-byte transmit FIFO buffer for endpoint 3. EPDR4 holds one packet of transmit data
for the interrupt transfer of endpoint 3. Transmit data is fixed by writing one packet of data and
setting EP3PKTE in the trigger register. When an ACK handshake is returned from the host after
the data has been transmitted, EP3TS in interrupt flag register 1 is set. This FIFO buffer can be
initialized by means of EP3CLR in the FCLR0 register.
Rev. 3.00 Jan. 18, 2008 Page 822 of 1458
REJ09B0033-0300
Bit
7 to 0 D7 to D0
Bit
7 to 0 D7 to D0
Bit
7 to 0 D7 to D0
Bit Name
Bit Name
Bit Name
USB Function Controller (USBF)
Initial Value R/W
Undefined
Initial Value R/W
Undefined
Initial Value R/W Description
Undefined
R
W
W
Description
Data register for interrupt transfer
Description
Data register for endpoint 2 transfer
Data register for endpoint 3 transfer