HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 369

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

• CS5BWCR
Bit
5 to 2
1
0
Bit
31 to 21
20
19
Bit Name

HW1
HW0
Bit Name

BAS

Initial
Value
All 0
0
0
Initial
Value
All 0
0
0
R/W
R
R/W
R
R/W
R
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
1: Asserts the WEn (BEn) signal during the read/write
Reserved
This bit is always read as 0. The write value should always
be 0.
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Number of Delay Cycles from RD, WEn (BEn) negation to
Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
and asserts the RD/WR signal during the write access
cycle.
access cycle and asserts the RD/WR signal at the write
timing.
Rev. 3.00 Jan. 18, 2008 Page 307 of 1458
Section 9
Bus State Controller (BSC)
REJ09B0033-0300