HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 768
HD6417320
Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
1.HD6417320.pdf
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Section 21
21.3.12 Receive Data Assign Register (SIRDAR)
SIRDAR is a 16-bit readable/writable register that specifies the position of the receive data in a
frame (slot number).
Rev. 3.00 Jan. 18, 2008 Page 706 of 1458
REJ09B0033-0300
Bit
15
14 to 12
11
10
9
8
7
6 to 4
3
2
1
0
Bit Name
RDLE
RDLA3
RDLA2
RDLA1
RDLA0
RDRE
RDRA3
RDRA2
RDRA1
RDRA0
Serial I/O with FIFO (SIOF)
Initial
Value
0
All 0
0
0
0
0
0
All 0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
Description
Receive Left-Channel Data Enable
0: Disables left-channel data reception
1: Enables left-channel data reception
Reserved
These bits are always read as 0. The write value should
always be 0.
Receive Left-Channel Data Assigns 3 to 0
Specify the position of left-channel data in a receive
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
•
Receive Right-Channel Data Enable
0: Disables right-channel data reception
1: Enables right-channel data reception
Reserved
These bits are always read as 0. The write value should
always be 0.
Receive Right-Channel Data Assigns 3 to 0
Specify the position of right-channel data in a receive
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
•
Receive data for the left channel is stored in the
SIRDL bit in SIRDR.
Receive data for the right channel is stored in the
SIRDR bit in SIRDR.
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