HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 764

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 21
Rev. 3.00 Jan. 18, 2008 Page 702 of 1458
REJ09B0033-0300
Bit
7
6
5
4
3
2
1
0
Bit Name
RFWM2
RFWM1
RFWM0
RFUA4
RFUA3
RFUA2
RFUA1
RFUA0
Serial I/O with FIFO (SIOF)
Initial
Value
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R
R
R
R
R
Description
Receive FIFO Watermark
000: Issue a transfer request when 1 stage or more of the
001: Setting prohibited
010: Setting prohibited
011: Setting prohibited
100: Issue a transfer request when 4 or more stages of
101: Issue a transfer request when 8 or more stages of
110: Issue a transfer request when 12 or more stages of
111: Issue a transfer request when 16 stages of the
•
•
Receive FIFO Usable Area
Indicate the number of words that can be transferred by
the CPU or DMAC as B'00000 (empty) to B'10000 (full).
A transfer request to the receive FIFO is issued by the
RDREQ bit in SISTR.
The receive FIFO is always used as 16 stages of the
FIFO regardless of these bit settings.
receive FIFO are valid.
the receive FIFO are valid.
the receive FIFO are valid.
the receive FIFO are valid.
receive FIFO are valid.