HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 566

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 14 Timer Unit (TMU)
Note:
14.2.3
TCOR set the value to be set in TCNT when TCNT underflows.
TCOR are 32-bit readable/writable registers.
TCOR are initialized to H'FFFFFFFF at a power-on reset or manual reset. They are retained in
standby or sleep mode.
14.2.4
TCNT count down upon input of a clock. The clock input is selected using the TPSC2 to TPSC0
bits in the timer control register (TCR).
When a TCNT count-down results in an underflow (H'00000000 → H'FFFFFFFF), the underflow
flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR value is
simultaneously set in TCNT itself and the count-down continues from that value.
TCNT are initialized to H'FFFFFFFF at a power-on reset or manual reset. They are retained in
standby or sleep mode.
Rev. 3.00 Jan. 18, 2008 Page 504 of 1458
REJ09B0033-0300
Bit
4, 3
2
1
0
*
Bit Name
—
TPSC2
TPSC1
TPSC0
Timer Constant Registers (TCOR)
Timer Counters (TCNT)
Only 0 can be written to clear the flag.
Initial
Value
All 0
0
0
0
R/W
R
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Timer Prescaler 2 to 0
Select the TCNT count clock.
000: Count on Pφ/4
001: Count on Pφ/16
010: Count on Pφ/64
011: Count on Pφ/256
101: Count on RTC output clock (16 kHz)
Others are setting prohibited.