HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1282

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 36
36.3
The H-UDI has the following registers. Refer to section 37, List of Registers, for more details on
the addresses and states of these registers in each operating mode.
• Bypass register (SDBPR)
• Instruction register (SDIR)
• Boundary scan register (SDBSR)
• ID register (SDID)
• Shift register
36.3.1
SDBPR is a 1-bit register that cannot be accessed by the CPU. When SDIR is set to the bypass
mode, SDBPR is connected between H-UDI pins TDI and TDO. The initial value is undefined.
36.3.2
SDIR is a 16-bit read-only register. The register is in JTAG IDCODE in its initial state. It is
initialized by TRST assertion or in the TAP test-logic-reset state, and can be written to by the H-
UDI irrespective of the CPU mode. Operation is not guaranteed if a reserved command is set in
this register.
Rev. 3.00
REJ09B0033-0300
Bit
15 to 13
12
11 to 8
7 to 2
1
0
Bypass Register (SDBPR)
Instruction Register (SDIR)
Register Descriptions
Jan. 18, 2008
Bit Name
TI7 to TI5
TI4
TI3 to TI0



User Debugging Interface (H-UDI)
All 1
All 1
Initial
Value
0
All 1
0
1
Page 1220 of 1458
R/W
R
R
R
R
R
R
Description
Test Instruction 7 to 0
The H-UDI instruction is transferred to SDIR by a serial
input from TDI.
For commands, see table 36.2.
Reserved
These bits are always read as 1.
Reserved
This bit is always read as 0.
Reserved
This bit is always read as 1.