HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1139

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

(6)
Flash memory operation commands include a number of commands involving write data. Such
commands confirm the card status by the command argument and command response, and
transmit card information and flash memory data from the DAT pin. For a command that is related
to time-consuming processing such as flash memory programming, the MMC indicates the data
busy state via the DAT pin.
For multiblock transfer, there are two methods. One is the open-ended method in which the
instruction for continuing/suspending the command sequence is made by suspending the transfer
for every block. Another one is the pre-defined method in which the transfer is performed after
setting the number of blocks to be transferred.
The command sequence is suspended when FIFO is full between the block transfers. When the
command sequence is suspended, data in the receive data FIFO is processed, if necessary, and the
command sequence is then continued.
Figures 31.15 to 31.18 show examples of the command sequence for commands with write data.
Figures 31.19 to 31.22 show the operational flowcharts for commands with write data.
• Settings needed to issue a command are made. The FIFO is cleared.
• The START bit in CMDSTRT is set to 1 to start command transmission.
• A command response is received from the MMC.
• If the MMC does not return the command response, the command response is detected by the
• Write data is set to the FIFO.
• The DATAEN bit in OPCR is set to start write data transmission.
• Suspension inter-blocks in multiblock transfer and suspension according to the FIFO empty are
• The end of the command sequence is detected by poling the BUSY flag in CSTR, data
• In addition, after the end of data transfer (after DRPI is detected), whether the data busy state
command timeout error (CTERI).
detected by the data response end interrupt flag (DRPI) and FIFO empty interrupt flag (FEI),
respectively. To continue the command sequence, data should be written to the FIFO, and the
DATAEN bit in OPCR should be set to 1. To end the command sequence, the CMDOFF bit in
OPCR should be set to 1, and the CMD12 should be issued. Note that the CMD12 is not
required other than when the sequence is suspended in pre-defined multiblock transfer.
response end flag (DPRI), or multiblock transfer (pre-defined) end flag (BTI).
is entered or not is determined by the DTBUSY bit in CSTR. If the data busy state is entered,
cancellation of the data busy state is detected by the data busy end interrupt (DBSYI).
Commands with Write Data
Section 31
Rev. 3.00 Jan. 18, 2008 Page 1077 of 1458
MultiMediaCard Interface (MMCIF)
REJ09B0033-0300