HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 422

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9
(3)
A burst read occurs in the following cases with this LSI.
1. Access size in reading is larger than data bus width.
2. 16-byte transfer in cache miss.
3. 16-byte transfer in DMAC or USDH(access to non-cacheable area)
4. 16- to 128-byte transfer by LCDC*
This LSI always accesses the SDRAM with burst length 1. For example, read access of burst
length 1 is performed consecutively four times to read 16-byte continuous data from the SDRAM
that is connected to a 32-bit data bus.
Table 9.18 shows the relationship between the access size and the number of bursts.
Note: * For details, see section 26, LCD Controller (LCDC).
Table 9.18 Relationship between Access Size and Number of Bursts
Figures 9.14 and 9.15 show a timing chart in burst read. In burst read, an ACTV command is
output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA
command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external
clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an
auto-precharge induced by the READ command in the SDRAM. In the Tap cycle, a new
command will not be issued to the same bank. However, access to another CS space or another
bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the TRP1
and TRP0 bits in CS3WCR.
Rev. 3.00 Jan. 18, 2008 Page 360 of 1458
REJ09B0033-0300
Bus Width
16 bits
32 bits
Burst Read
Bus State Controller (BSC)
Access Size
8 bits
16 bits
32 bits
16 bytes
128 bytes
8 bits
16 bits
32 bits
16 bytes
128 bytes
Number of Bursts
1
1
2
8
64
1
1
1
4
32