HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 586

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 15
15.3.5
The TSR registers are 16-bit registers that indicate the status of each channel. The TPU has four
TSR registers, one for each channel. The TSR registers are initialized to H'0000 by a reset, but not
initialized in standby mode, sleep mode or module standby mode.
Rev. 3.00 Jan. 18, 2008 Page 524 of 1458
REJ09B0033-0300
Bit
1
0
Bit
15 to 8 
7
6
Bit Name
TG1EB
TG1EA
Bit Name
TCFD

Timer Status Registers (TSR)
16-Bit Timer Pulse Unit (TPU)
Initial
Value
0
0
Initial
Value R/W
All 0
0
0
R
R
R
R/W
R/W
R/W
Description
TGR Interrupt Enable B
Enables or disables interrupt requests by the TGFB bit when
the TGFB bit in TSR is set to 1 (TCNT and TGRB compare
match).
0: Interrupt requests by TGFB disabled
1: Interrupt requests by TGFB enabled
TGR Interrupt Enable A
Enables or disables interrupt requests by the TGFA bit when
the TGFA bit in TSR is set to 1 (TCNT and TGRA compare
match).
0: Interrupt requests by TGFA disabled
1: Interrupt requests by TGFA enabled
Description
Reserved
These bits are always read as 0 and cannot be modified.
Count Direction Flag
Status flag that shows the direction in which TCNT counts in
phase counting mode of channels 2, and 3.
In channels 0 and 1, bit 7 is reserved. It is always read as 0
and cannot be modified.
0: TCNT counts down
1: TCNT counts up
Reserved
This bit is always read as 0 and cannot be modified.