HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 182

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 3 DSP Operating Unit
Table 3.19 DC Bit Update Definitions
Rev. 3.00 Jan. 18, 2008 Page 120 of 1458
REJ09B0033-0300
CS [2:0] Condition Mode
0 0 0 Carry or borrow
0 0 1 Negative value
0 1 0 Zero value mode
0 1 1 Overflow mode
1 0 0 Signed greater-than
1 0 1 Signed greater-or-
1 1 0 Reserved (setting prohibited)
1 1 1 Reserved (setting prohibited)
mode
mode
mode
equal mode
Description
The DC bit is set if an ALU arithmetic operation generates a carry
or borrow, and is cleared otherwise.
When a PSHA or PSHL shift instruction is executed, the last bit
data shifted out is copied into the DC bit.
When an ALU logical operation is executed, the DC bit is always
cleared.
When an ALU or shift (PSHA) arithmetic operation is executed,
the MSB of the result, including the guard bits, is copied into the
DC bit.
When an ALU or shift (PSHL) logical operation is executed, the
MSB of the result, excluding the guard bits, is copied into the DC
bit.
The DC bit is set if the result of an ALU or shift operation is all-
zeros, and is cleared otherwise.
The DC bit is set if the result of an ALU or shift (PSHA) arithmetic
operation exceeds the destination register range, excluding the
guard bits, and is cleared otherwise.
When an ALU or shift (PSHL) logical operation is executed, the
DC bit is always cleared.
This mode is similar to signed greater-or-equal mode, but DC is
cleared if the result is all-zeros.
DC = ~{(negative value ^ over-range) | zero value};
DC = 0; In case of logical operation
If the result of an ALU or shift (PSHA) arithmetic operation
exceeds the destination register range, including the guard bits
(over-range), the definition is the same as in negative value mode.
If the result is not over-range, the definition is the opposite of that
in negative value mode.
When an ALU or shift (PSHL) logical operation is executed, the
DC bit is always cleared.
DC = ~(negative value ^ over-range);
DC = 0 ; In case of logical operation
In case of arithmetic operation
In case of arithmetic operation