HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 870

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 25
25.3.1
IFR0 is an interrupt flag register for EP0i, EP0o, EP1, EP2, bus reset, and setup command
reception. When each flag is set to 1 and the interrupt is enabled in the corresponding bit of IER0,
an interrupt request is generated as specified by the corresponding bit in ISR0. Clearing is
performed by writing 0 to the bit to be cleared. Writing 1 is not valid and nothing is changed.
EP2 EMPTY and EP1 FULL are status bits that indicate the FIFO states of EP1 and EP2,
respectively. Therefore, EP2 EMPTY and EP1 FULL cannot be cleared.
Rev. 3.00 Jan. 18, 2008 Page 808 of 1458
REJ09B0033-0300
Bit
7
6
5
Bit Name
BRST
EP1 FULL
EP2 TR
Interrupt Flag Register 0 (IFR0)
USB Function Controller (USBF)
Initial Value
0
0
0
R/W Description
R/W Bus Reset
R
R/W EP2 (Bulk-in) Transfer Request
[Setting condition]
When a bus reset signal is detected on the USB bus.
[Clearing conditions]
•
•
EP1 (Bulk-out) FIFO Full
[Setting condition]
The FIFO buffer of EP1 has a dual-buffer
configuration, and this bit is set when at least one of
the FIFO buffer is full.
[Setting conditions]
•
•
Note: EP1 FULL is a status bit, and cannot be
[Setting condition]
When an IN token is received from the host to EP2
and both of FIFO buffers are empty.
[Clearing conditions]
•
•
When reset
When 0 is written to by CPU
When reset
When both FIFO buffers are empty.
When reset
When 0 is written to by CPU
cleared.