HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1468
HD6417320
Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
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Rev. 3.00 Jan. 18, 2008 Page 1406 of 1458
REJ09B0033-0300
Item
9.4.4 SDRAM Control Register
(SDCR)
9.5.5 SDRAM Interface
(10) Low-Frequency Mode
9.5.7 Byte-Selection SRAM
Interface
Figure 9.34 Wait Timing for Byte-
Selection SRAM (BAS = 1)
(Software Wait Only)
Figure 9.36 Example of
Connection with 16-Bit Data-Width
Byte-Selection SRAM
9.5.8 PCMCIA Interface
(1) Basic Timing for Memory Card
Interface
Page Revision (See Manual for Details)
326
390
391
395
Amended
Deleted
Changed
Changed
Changed
If all 32 Mbytes of the memory space are used as an IC
memory card interface, the REG signal that switches
between the common memory and attribute memory
can be generated by an I/O port.
Bit
12
11
Bit
Name
RFSH
A25 to A0
CKIO
R/W
R
R/W
Th
Description
Reserved
This bit is always read as 0. The
write value should always be 0.
Refresh Control
Specifies whether or not the refresh
operation of the SDRAM is
performed.
0: No refresh
1: Refresh
T1
A15
A0
CS
OE
WE
I/O15
I/O0
UB
LB
Tw
64Kx16bit
SRAM
T2
Tf
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