HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 707

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

The I
functions. The register configuration that controls the I
configuration, however.
Figure 20.1 shows a block diagram of the I
Figure 20.2 shows an example of I/O pin connections to external circuits.
20.1
• Continuous transmission/reception
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization/wait function
• Six interrupt sources
• Direct bus drive
IFIIC10A_000020020200
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically.
If transmission/reception is not yet possible, set the SCL to low until preparations are
completed.
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive
function is selected.
2
C bus interface supports and provides a subset of the Philips I
Features
Section 20
I
2
2
C bus interface.
C Bus Interface (IIC)
2
C bus differs partly from the Philips
Rev. 3.00 Jan. 18, 2008 Page 645 of 1458
2
Section 20
C bus (inter-IC bus) interface
I
2
C Bus Interface (IIC)
REJ09B0033-0300