HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 734

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 20
Rev. 3.00 Jan. 18, 2008 Page 672 of 1458
REJ09B0033-0300
No
No
No
Clear ACKBT in ICIER to 0
Clear RCVD in ICCR1 to 0
Set ACKBT in ICIER to 1
Clear MST in ICCR1 to 0
Clear TRS in ICCR1 to 0
Set RCVD in ICCR1 to 1
Clear STOP in ICSR.
Clear TEND in ICSR
Clear TDRE in ICSR
Dummy-read ICDRR
Read RDRF in ICSR
Read RDRF in ICSR
Read STOP in ICSR
I
Mater receive mode
2
C Bus Interface (IIC)
Write 0 to BBSY
Read ICDRR
Read ICDRR
Read ICDRR
Last receive
RDRF=1 ?
RDRF=1 ?
STOP=1 ?
and SCP
- 1?
End
Figure 20.15
Yes
Yes
Yes
No
Yes
Sample Flowchart for Master Receive Mode
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
Note: 1. Do not activate an interrupt during the execution of steps [1] to [3].
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10] Clear the STOP flag.
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
[13] Read the last byte of receive data.
[14] Clear RCVD.
[15] Set slave receive mode.
Clear TEND, select master receive mode, and then clear TDRE.*
Set acknowledge to the transmit device.*
Dummy-read ICDDR.*
Wait for 1 byte to be received
Check whether it is the (last receive - 1).
Read the receive data last.
Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
Read the (final byte - 1) of receive data.
Wait for the last byte to be receive.
2. When one byte is received, steps [2] to [6] are skipped; step [7] is executed
after step [1]. Setp [8] is ICDRR dummy read.
1
1
*
2