HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 462

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9
9.5.9
The burst ROM (clock synchronous) interface is supported to access a ROM with a synchronous
burst function at high speed. The burst ROM interface accesses the burst ROM in the same way as
a normal space. This interface is valid only for area 0.
In the first access cycle, wait cycles are inserted. In this case, the number of wait cycles to be
inserted is specified by the W[3:0] bits of the CS0WCR. In the second and subsequent cycles, the
number of wait cycles to be inserted is specified by the BW[1:0] bits of the CS0WCR.
While the burst ROM is accessed (clock synchronous), the BS signal is asserted only for the first
access cycle and an external wait input is also valid for the first access cycle.
If the bus width is 16 bits, the burst length must be specified as 8. If the bus width is 32 bits, the
burst length must be specified as 4. The burst ROM interface does not support the 8-bit bus width
for the burst ROM. The burst ROM interface performs burst operations for all read accesses. For
example, in a longword access over a 16-bit bus, valid 16-bit data is read two times and invalid
16-bit data is read six times.
These invalid data read cycles increase the memory access time and degrade the program
execution speed and DMA transfer speed. To prevent this problem, a 16-byte read by cache fill or
16-byte read by the DMA should be used. The burst ROM interface performs write accesses in the
same way as normal space access.
Rev. 3.00 Jan. 18, 2008 Page 400 of 1458
REJ09B0033-0300
D15 to D0
Address
DACKn*
RD/WR
WAIT
CKIO
CSn
RD
BS
Note: The waveform for DACKn is when active low is specified.
T1
Burst ROM (Clock Synchronous) Interface
Bus State Controller (BSC)
Tw
Figure 9.44
Wait Cycles inserted in Second and Subsequent Accesses = 1)
(Burst Length = 8, Wait Cycles inserted in First Access = 2,
Tw
T2B
Twb
Burst ROM (Clock Synchronous) Access Timing
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2