HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 189
HD6417320
Manufacturer Part Number
HD6417320
Description
Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
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Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. However, in case of a conditional
operation, they are not updated even though the specified condition is true and the operation is
executed. In case of an unconditional operation, they are always updated in accordance with the
operation result. The definition of a DC bit is selected by CS[2:0] (condition selection) bits in
DSR. The DC bit result is as follows:
Operation Sequence Example
PADD X0, Y0, A0
Stage
MA/DSP
EX
ID
IF
Slot
MOVX.W @R4 + X0
MOVX.W @R4 + X0
MOVX
Figure 3.10 Operation Sequence Example
1
MOVX & PADD
MOVX
2
Previous cycle result is used.
MOVX & PADD
Addressing
3
Addressing
MOVX
Rev. 3.00 Jan. 18, 2008 Page 127 of 1458
4
MOVX & PADD
Section 3 DSP Operating Unit
5
REJ09B0033-0300
6
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