HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 535

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

12.2.3
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are
more difficult to write to than other registers. The procedure for writing to these registers is given
below.
• Writing to WTCNT and WTCSR
Bit
2
1
0
These registers must be written by a word transfer instruction. They cannot be written by a
byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A
and transfer the lower byte as the write data, as shown in figure 12.3. When writing to
WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer
procedure writes the lower byte data to WTCNT or WTCSR.
Bit Name
CKS2
CKS1
CKS0
Notes on Register Access
Initial
Value
0
0
0
R/W
R/W
R/W
R/W
Description
Clock Select 2 to 0
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock (Pφ). The overflow period that is shown
inside the parenthesis in the table is the value when the
peripheral clock (Pφ) is 15 MHz.
000: Pφ (17 µs)
001: Pφ /4 (68 µs)
010: Pφ /16 (273 µs)
011: Pφ /32 (546 µs)
100: Pφ /64 (1.09 ms)
101: Pφ /256 (4.36 ms)
110: Pφ /1024 (17.48 ms)
111: Pφ /4096 (69.91 ms)
Note: If bits CKS2 to CKS0 are modified when the WDT
is operating, the up-count may not be performed
correctly. Ensure that these bits are modified only
when the WDT is not operating.
Rev. 3.00 Jan. 18, 2008 Page 473 of 1458
Section 12 Watchdog Timer (WDT)
REJ09B0033-0300