HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 476

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 10
Rev. 3.00 Jan. 18, 2008 Page 414 of 1458
REJ09B0033-0300
Bit
16
15
14
13
12
Bit Name
AL
DM1
DM0
SM1
SM0
Direct Memory Access Controller (DMAC)
Initial
Value
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Descriptions
Acknowledge Level
Specifies whether the DACK signal output is high active
or low active.
This bit is valid only in CHCR_0 and CHCR_1. This bit
is always reserved and read as 0 in CHCR_2 to
CHCR_5. The write value should always be 0.
0: Low-active output of DACK
1: High-active output of DACK
Destination Address Mode 1, 0
Specify whether the DMA destination address is
incremented, decremented, or left fixed. (In single
address mode, the DM1 and DM0 bits are ignored
when data is transferred to an external device with
DACK.)
00: Fixed destination address (setting prohibited in 16-
01: Destination address is incremented (+1 in byte-unit
10: Destination address is decremented (–1 in byte-unit
11: Setting prohibited
Source Address Mode 1, 0
Specify whether the DMA source address is
incremented, decremented, or left fixed. (In single
address mode, SM1 and SM0 bits are ignored when
data is transferred from an external device with DACK.)
00: Fixed source address (setting prohibited in 16-byte
01: Source address is incremented (+1 in byte-unit
10: Source address is decremented (–1 in byte-unit
11: Setting prohibited
byte transfer)
transfer, +2 in word-unit transfer, +4 in longword-
unit transfer, +16 in 16-byte transfer)
transfer, –2 in word-unit transfer, –4 in longword-
unit transfer; setting prohibited in 16-byte transfer)
transfer)
transfer, +2 in word-unit transfer, +4 in longword-
unit transfer, +16 in 16-byte transfer)
transfer, –2 in word-unit transfer, –4 in longword-
unit transfer; setting prohibited in 16-byte transfer)