HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1491

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Item
31.3.19 DMA Control Register
(DMACR)
31.4 Operation
31.4.1 Operations in MMC Mode
(1) Operation of Broadcast
Commands
(4) Operation of Commands
without Data Transfer
Figure 31.5 Example of Command
Sequence for Commands without
Data Transfer (with Data Busy
State)
1055 Restrictions added
1059 Deleted
1062 Corrected
1064 Changed
Page Revision (See Manual for Details)
Set this register before executing a multiblock transfer
command (CMD18 or CMD25). Auto mode cannot be
used for open-ended multiblock transfer.
…In this case, the transfer clock of CLKON should be
divided by 100 and the transfer clock frequency should
be set sufficiently slow.
Corrected and deleted
The individual MMC compares its CID and data on the
MMC_CMD, and if different, aborts CID output. A single
MMC in which the CID can be entirely output enters the
acknowledge state. When the R2 response is
necessary, CTOCR should be set to H'01.
For a command that is related to time-consuming
processing such as flash memory write/erase, the MMC
indicates the data busy state via the MMC_DAT.
…
• Whether the data busy state is entered or not is
determined by the DTBUSY bit in CSTR. …
(DTBUSY_TU)
(DTBUSY)
(BUSY)
(REQ)
Rev. 3.00 Jan. 18, 2008 Page 1429 of 1458
Command sequence execution period
REJ09B0033-0300
Data busy period