HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 888

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 25
25.3.30 FIFO Clear Register 1 (FCLR1)
FCLR is a one shot register to clear the FIFO buffers for endpoints 4 and 5. Writing 1 to a bit
clears the data in the corresponding FIFO buffer.
The corresponding interrupt flag is not cleared by this clear instruction. Do not clear a FIFO buffer
during transmission and reception.
25.3.31 DMA Transfer Setting Register (DMA)
DMA is set when the dual address transfer is used to the data register for endpoints 1 and 2 to
which transfer is possible by DMA. The USB1_pwr_en pin level can be controlled by the bit 2.
Rev. 3.00 Jan. 18, 2008 Page 826 of 1458
REJ09B0033-0300
Bit
3, 2
1
0
Bit
7 to 5 
4
3, 2
1
0
Bit
7 to 3 
2
Bit Name

EP0o CLR
EP0i CLR
Bit Name
EP5 CCLR

EP5 CLR
EP4 CLR
Bit Name
PULLUP E
USB Function Controller (USBF)
Initial Value R/W



Initial Value R/W Description





Initial Value R/W Description
All 0
0
W
W
W
W
W
W
W
W
R
R/W Pull-up Enable
Description
Reserved
The write value should always be 0.
EP0o Clear
EP0i Clear
Reserved
EP5 CPU Clear
Reserved
EP5 Clear
EP4 Clear
The write value should always be 0.
The write value should always be 0.
Reserved
These bits are always read as 0. The write value
should always be 0.
Controls connection notification to USB host/hub.
0: USB1_pwr_en pin goes high
1: USB1_pwr_en pin goes low