HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 269

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

5.3.2
(1)
In a read access, instructions and data are transferred from the cache to the CPU. The LRU i
updated to indicate that the hit way is the most recently hit way.
(2)
An external bus cycle starts and the entry is updated. The way to be replaced is shown in table 5.4.
Entries are updated in 16-byte units. When the desired instruction or data that caused the miss is
loaded from external memory to the cache, the instruction or data is transferred to the CPU in
parallel with being loaded to the cache. When it is loaded to the cache, the U bit is cleared to 0 and
the V bit is set to 1 to indicate that the hit way is the most recently hit way. When the U bit for the
entry which is to be replaced by entry updating in write-back mode is 1, the cache-update cycle
starts after the entry is transferred to the write-back buffer. After the cache completes its update
cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte units.
5.3.3
(1)
The LRU is updated to indicate that the hit way is the most recently hit way. The other contents of
the cache are not changed. Instructions and data are not transferred from the cache to the CPU.
(2)
Instructions and data are not transferred from the cache to the CPU. The way that is to be replaced
is shown in table 5.3. The other operations are the same as those for a read miss.
5.3.4
(1)
In a write access in write-back mode, the data is written to the cache and no external memory
write cycle is issued. The U bit of the entry that has been written to is set to 1, and the LRU is
updated to indicate that the hit way is the most recently hit way. In write-through mode, the data is
written to the cache and an external memory write cycle is issued. The U bit of the entry that has
been written to is not updated, and the LRU is updated to indicate that the hit way is the most
recently hit way.
Read Hit
Read Miss
Prefetch Miss
Write Hit
Prefetch Hit
Read Access
Prefetch Operation
Write Access
Rev. 3.00 Jan. 18, 2008 Page 207 of 1458
REJ09B0033-0300
Section 5 Cache
s