HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 14

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 X/Y Memory ....................................................................................... 213
6.1
6.2
6.3
Section 7 Exception Handling ............................................................................. 217
7.1
7.2
7.3
7.4
7.5
Section 8 Interrupt Controller (INTC)................................................................. 243
8.1
8.2
8.3
Rev. 3.00 Jan. 18, 2008 Page xiv of lxii
Features.............................................................................................................................. 213
Operation ........................................................................................................................... 214
6.2.1
6.2.2
6.2.3
Usage Notes ....................................................................................................................... 215
6.3.1
6.3.2
6.3.3
6.3.4
Register Descriptions......................................................................................................... 217
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
Exception Handling Function ............................................................................................ 221
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
Individual Exception Operations ....................................................................................... 227
7.3.1
7.3.2
7.3.3
Exception Processing While DSP Extension Function is Valid......................................... 234
7.4.1
7.4.2
7.4.3
Usage Notes ....................................................................................................................... 241
Features.............................................................................................................................. 243
Input/Output Pins............................................................................................................... 245
Register Descriptions......................................................................................................... 246
Access from CPU ................................................................................................. 214
Access from DSP.................................................................................................. 214
Access from Bus Master Module.......................................................................... 215
Page Conflict ........................................................................................................ 215
Bus Conflict .......................................................................................................... 215
MMU and Cache Settings..................................................................................... 216
Sleep Mode ........................................................................................................... 216
TRAPA Exception Register (TRA) ...................................................................... 218
Exception Event Register (EXPEVT)................................................................... 219
Interrupt Event Register (INTEVT)...................................................................... 219
Interrupt Event Register 2 (INTEVT2)................................................................. 220
Exception Address Register (TEA) ...................................................................... 220
Exception Handling Flow ..................................................................................... 221
Exception Vector Addresses................................................................................. 222
Exception Codes ................................................................................................... 222
Exception Request and BL Bit (Multiple Exception Prevention) ......................... 222
Exception Source Acceptance Timing and Priority .............................................. 223
Resets.................................................................................................................... 227
General Exceptions............................................................................................... 227
General Exceptions (MMU Exceptions)............................................................... 231
Illegal Instruction Exception and Illegal Slot Instruction Exception .................... 234
CPU Address Error ............................................................................................... 234
Exception in Repeat Control Period ..................................................................... 234