HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 903

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

• Data Stage (Control-In)
The application first analyzes command data from the host in the setup stage, and determines the
subsequent data stage direction. If the result of command data analysis is that the data stage is in-
transfer, one packet of data to be sent to the host is written to the FIFO. If there is more data to be
sent, this data is written to the FIFO after the data written first has been sent to the host
(IFR0/EP0i TS = 1).
The end of the data stage is identified when the host transmits an OUT token and the status stage
is entered.
Note: If the size of the data transmitted by the function is smaller than the data size requested by
the host, the function indicates the end of the data stage by returning to the host a packet
shorter than the maximum packet size. If the size of the data transmitted by the function is
an integral multiple of the maximum packet size, the function indicates the end of the data
stage by transmitting a zero-length packet.
Data transmission to host
Set EP0i transmission
(IFR0/EP0i TS = 1)
IN token reception
USB function
in EP0i FIFO?
complete flag
to TRG/EP0s
Figure 25.7
Valid data
1 written
RDFN?
Yes
Yes
ACK
Data Stage (Control-In) Operation
No
No
NAK
NAK
Interrupt request
Section 25
Rev. 3.00 Jan. 18, 2008 Page 841 of 1458
Clear EP0i transmission
data register (EPDR0i)
data register (EPDR0i)
Write 1 to EP0i packet
Write 1 to EP0i packet
(TRG/EP0i PKTE = 1)
(TRG/EP0i PKTE = 1)
(IFR0/EP0i TS = 0)
Write data to EP0i
Write data to EP0i
From setup stage
complete flag
Application
enable bit
enable bit
USB Function Controller (USBF)
REJ09B0033-0300