HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 726

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 20
6. When the RDRF bit is set to 1 at rise of the 9th receive clock pulse, issue the stage condition.
7. When the STOP bit in ICSR is set to 1, read ICDRR. Then clear the RCVD bit to 0.
8. The operation returns to the slave receive mode.
Rev. 3.00 Jan. 18, 2008 Page 664 of 1458
REJ09B0033-0300
(Master output)
(Master output)
(Slave output)
Master transmit mode
processing
ICDRS
ICDRR
TDRE
TEND
RDRF
User
TRS
SCL
SDA
SDA
I
2
C Bus Interface (IIC)
[1] Clear TDRE after clearing
Figure 20.7
TEND and TRS
A
9
Bit 7
Master Receive Mode Operation Timing (1)
1
Master receive mode
[2] Read ICDRR (dummy read)
2
Bit 6
3
Bit 5
4
Bit 4
5
Bit 3
6
Bit 2
7
Bit 1
Data 1
8
Bit 0
[3] Read ICDRR
A
9
Bit 7
Data 1
1