HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 1054

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 30
30.3.3
SCSCR is an 8-bit readable/writable register that selects transmit or receive operation, the serial
clock output, and whether to enable or disable interrupt requests for the smart card interface.
Rev. 3.00 Jan. 18, 2008 Page 992 of 1458
REJ09B0033-0300
Bit
7
6
Bit Name
TIE
RIE
Serial Control Register (SCSCR)
SIM Card Module (SIM)
Initial
Value
0
0
R/W
R/W
R/W
Description
Transmit Interrupt Enable
When serial transmit data is transferred from the transmit
data register (SCTDR) to the transmit shift register
(SCTSR), and the TDRE flag in the serial status register
(SCSSR) is set to 1, transmit data empty interrupt (TXI)
requests are enabled/disabled.
0: Disables transmit data empty interrupt (TXI) requests*
1: Enables transmit data empty interrupt (TXI) requests
Note: * A TXI can be canceled either by clearing the
Receive Interrupt Enable
When serial receive data is transferred from the receive
shift register (SCRSR) to the receive data register
(SCRDR), and the RDRF flag in SCSSR is set to 1, receive
data full interrupt (RXI) requests, and transmit/receive error
interrupt (ERI) requests due to parity errors, overrun errors,
and error signal status are enabled/disabled.
0: Disables receive data full interrupt (RXI) requests and
1: Enables receive data full interrupt (RXI) requests and
Notes:
transmit/receive error interrupt (ERI) requests*
transmit/receive error interrupt (ERI) requests*
TDRE flag, or by clearing the TIE bit to 0.
1. RXI and ERI interrupt requests can be
2. Wait error interrupt (ERI) requests are enabled
canceled either by clearing the RDRF, PER,
ORER or ERS flag, or by clearing the RIE bit to
0.
or disabled by using the WAIT_IE bit in
SCSCR.
1
2
*
2