HD6417320 RENESAS [Renesas Technology Corp], HD6417320 Datasheet - Page 128

• Manufacturer Part Number: HD6417320
• Description: Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7700 Series
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 2
Notes: 1. The table shows the minimum number of execution states. In practice, the number of
Rev. 3.00 Jan. 18, 2008 Page 66 of 1458
REJ09B0033-0300
Instruction
Indicated by mnemonic.
Explanation of Symbols
OP.Sz SRC, DEST
Rm: Source register
Rn:
imm: Immediate data
disp: Displacement
OP:
Sz:
SRC: Source
DEST: Destination
Destination register
Operation code
Size
2. Scaled (x1, x2, or x4) according to the instruction operand size, etc.
CPU
a.
b.
instruction execution states will be increased in cases such as the following:
When there is a conflict between an instruction fetch and a data access
When the destination register of a load instruction (memory → register) is also
used by the following instruction
Instruction Code
Indicated in MSB ↔
LSB order.
Explanation of Symbols
mmmm: Source register
nnnn: Destination register
iiii:
dddd:
0000: R0
0001: R1
.........
1111: R15
Immediate data
Displacement *
2
Operation
Indicates summary of
operation.
Explanation of Symbols
→, ←: Transfer direction
(xx):
M/Q/T: Flag bits in SR
&:
|:
^:
~:
<<n: n-bit left shift
>>n: n-bit right shift
Logical AND of each bit
Logical OR of each bit
Exclusive logical OR of
each bit
Logical NOT of each bit
Memory operand
Privilege
Indicates a
privileged
instruction.
Execution
States
Value
when no
wait states
are
inserted *
1
T Bit
Value of T
bit after
instruction
is executed
Explanation
of Symbols

change
: No