sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 99

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Freescale Semiconductor
DDRH
DDRH
DDRH
DDRH
DDRH
Field
7-4
3
2
1
0
Port H data direction—
This register controls the data direction of pin 7-4.
If enabled the LCD segment output it will force the I/O state to be a input/output diabled.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 3.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the IIC is routing to PH and IIC is enabled, the IIC will determined the pin direction
Else if the SPI is routing to PH and SPI is enabled, the SPI will determine the pin direction
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 2.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the SPI is routing to PH and SPI is enabled, the SPI will determine the pin direction
Else if ECLK is enabled, it will force the pin to output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 1.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the SPI is routing to PH and SPI is enabled, the SPI will determine the pin direction.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Port H data direction—
This register controls the data direction of pin 0.
If enabled the LCD segment output it will force the I/O state to be a input/output disabled
Else if the IIC is routing to PH and IIC is enabled, the IIC will determined the pin direction
Else if the SPI is routing to PH and SPI is enabled, the SPI will determine the pin direction t.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTH or PTIH registers, when changing the
DDRH register.
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-38. DDRH Register Field Descriptions
NOTE
Description
Port Integration Module (S12HYPIMV1)
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