sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 174

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Background Debug Module (S12SBDMV1)
The receive cases are more complicated.
system. Since the host is asynchronous to the target, there is up to one clock-cycle delay from the
host-generated falling edge on BKGD to the perceived start of the bit time in the target. The host holds the
BKGD pin low long enough for the target to recognize it (at least two target clock cycles). The host must
release the low drive before the target drives a brief high speedup pulse seven target clock cycles after the
perceived start of the bit time. The host should sample the bit level about 10 target clock cycles after it
started the bit time.
174
Start of Bit Time
Start of Bit Time
Target System
(Target MCU)
(Target MCU)
BDM Clock
BDM Clock
BKGD Pin
BKGD Pin
Transmit 1
Transmit 0
Perceived
Perceived
Speedup
Drive to
Pulse
Host
Host
Host
Synchronization
Uncertainty
Figure 5-8. BDM Target-to-Host Serial Bit Timing (Logic 1)
High-Impedance
Figure 5-7. BDM Host-to-Target Serial Bit Timing
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
10 Cycles
R-C Rise
Figure 5-8
10 Cycles
10 Cycles
shows the host receiving a logic 1 from the target
Target Senses Bit
Host Samples
High-Impedance
BKGD Pin
High-Impedance
Freescale Semiconductor
Next Bit
Earliest
Start of
Next Bit
Earliest
Start of