sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 172

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Background Debug Module (S12SBDMV1)
The external host should wait for at least for 76 bus clock cycles after a TRACE1 or GO command before
starting any new serial command. This is to allow the CPU to exit gracefully from the standard BDM
firmware lookup table and resume execution of the user code. Disturbing the BDM shift register
prematurely may adversely affect the exit from the standard BDM firmware lookup table.
Figure 5-6
times starting with a falling edge. The bar across the top of the blocks indicates that the BKGD line idles
in the high state. The time for an 8-bit command is 8 16 target clock cycles.
1. Target clock cycles are cycles measured using the target MCU’s serial clock rate. See
172
and
Section 5.3.2.1, “BDM Status Register (BDMSTS)”
Hardware
Hardware
Firmware
Firmware
TRACE
Read
Read
Write
Write
GO,
represents the BDM command structure. The command blocks illustrate a series of eight bit
If the bus rate of the target processor is unknown or could be changing, it is
recommended that the ACK (acknowledge function) is used to indicate
when an operation is complete. When using ACK, the delay times are
automated.
AT ~16 TC/Bit
Command
Command
Command
Command
Command
8 Bits
DELAY
48-BC
76-BC
Delay
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
AT ~16 TC/Bit
Figure 5-6. BDM Command Structure
Address
Address
16 Bits
Data
Command
Next
Data
for information on how serial clock rate is selected.
DELAY
36-BC
NOTE
150-BC
Delay
Command
Command
Next
Next
Data
AT ~16 TC/Bit
16 Bits
Data
BC = Bus Clock Cycles
TC = Target Clock Cycles
Section 5.4.6, “BDM Serial Interface”
150-BC
Delay
1
Freescale Semiconductor
Command
Command
Next
Next