sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 74

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

1
1
Port Integration Module (S12HYPIMV1)
2.3.7
2.3.8
74
Address 0x0004 (PRR) to 0x0007 (PRR)
Address 0x000C (PRR)
Read: Always reads 0x00
Write: Unimplemented
Read:Anytime in single-chip modes.
Write:Anytime, except BKPUE which is writable in Special Single-Chip Mode only.
DDRB
Field
Reset
Reset
7-0
W
W
R
R
Port B Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
1 Associated pin is configured as output
0 Associated pin is configured as input
PIM Reserved Register
Ports A, B, BKGD pin Pull Control Register (PUCR)
0
0
0
0
7
7
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTA, PTB registers, when changing the
DDRA,DDRB register.
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 2-6. Ports AB, BKGD pin Pull Control Register (PUCR)
BKPUE
0
0
1
6
6
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-7. DDRB Register Field Descriptions
Figure 2-5. PIM Reserved Register
0
0
0
0
5
5
NOTE
0
0
0
0
4
4
Description
3
0
0
3
0
0
0
0
0
0
2
2
Freescale Semiconductor
PUPBE
Access: User read/write
0
0
1
1
1
Access: User read
PUPAE
0
0
1
0
0
1
1