sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 354

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Freescale’s Scalable Controller Area Network (S12MSCANV3)
Due to independent clock domains within the MSCAN, INITRQ must be synchronized to all domains by
using a special handshake mechanism. This handshake causes additional synchronization delay (see
Section Figure 9-45., “Initialization Request/Acknowledge
If there is no message transfer ongoing on the CAN bus, the minimum delay will be two additional bus
clocks and three additional CAN clocks. When all parts of the MSCAN are in initialization mode, the
INITAK flag is set. The application software must use INITAK as a handshake indication for the request
(INITRQ) to go into initialization mode.
9.4.5
If the MSCAN is disabled (CANE = 0), the MSCAN clocks are stopped for power saving.
If the MSCAN is enabled (CANE = 1), the MSCAN has two additional modes with reduced power
consumption, compared to normal mode: sleep and power down mode. In sleep mode, power consumption
is reduced by stopping all clocks except those to access the registers from the CPU side. In power down
mode, all clocks are stopped and no power is consumed.
Table 9-38
is entered by the given settings on the CSWAI and SLPRQ/SLPAK bits.
354
summarizes the combinations of MSCAN and CPU modes. A particular combination of modes
Low-Power Options
The CPU cannot clear INITRQ before initialization mode (INITRQ = 1 and
INITAK = 1) is active.
Bus Clock Domain
CPU
Init Request
INITAK
Flag
Figure 9-45. Initialization Request/Acknowledge Cycle
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
INITRQ
sync.
INITAK
NOTE
SYNC
SYNC
Cycle”).
CAN Clock Domain
sync.
INITRQ
INITAK
INIT
Flag
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