sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 112

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

1
1
1
Port Integration Module (S12HYPIMV1)
2.3.64
2.3.65
2.3.66
112
Address 0x0287
Address 0x0288
Address 0x0289
Read: Always reads 0x00
Write: Unimplemented
Read: Anytime.
Write: Anytime.
Read: Anytime.
Write: Anytime.
Read: Anytime.
Field
PIET
Reset
Reset
Reset
7-0
W
W
W
R
R
R
Port T interrupt enable—
This register disables or enables on a per-pin basis the edge sensitive external interrupt associated with Port T.
1 Interrupt is enabled.
0 Interrupt is disabled (interrupt flag masked).
PIET7
PIFT7
PIM Reserved Registers
Port T Interrupt Enable Register (PIET)
Port T Interrupt Flag Register (PIFT)
0
0
0
0
7
7
7
= Unimplemented or Reserved
PIET6
PIFT6
0
0
0
0
6
6
6
Figure 2-63. Port T Interrupt Enable Register (PIET)
Figure 2-64. Port T Interrupt Flag Register (PIFT)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 2-54. PIET Register Field Descriptions
Figure 2-62. PIM Reserved Registers
PIET5
PIFT5
0
0
0
0
5
5
5
PIET4
PIFT4
0
0
0
0
4
4
4
Description
u = Unaffected by reset
PIET3
PIFT3
3
0
0
3
0
3
0
PIET2
PIFT2
0
0
0
0
2
2
2
Freescale Semiconductor
Access: User read/write
Access: User read/write
PIET1
PIFT1
0
0
0
0
1
1
1
Access: User read
PIET0
PIFT0
0
0
0
0
0
0
0
1
1
1