sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 231

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sc9s12hy64j0vllr

Manufacturer Part Number
sc9s12hy64j0vllr
Description
S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Figure 7-2
7.2
This section lists and describes the signals that connect off chip.
7.2.1
RESET is an active-low bidirectional pin. As an input it initializes the MCU asynchronously to a known
start-up state. As an open-drain output it indicates that an MCU-internal reset has been triggered.
7.2.2
These pins provide the interface for a crystal to control the internal clock generator circuitry. EXTAL is
the external clock input or the input to the crystal oscillator amplifier. XTAL is the output of the crystal
oscillator amplifier. The MCU internal OSCCLK is derived from the EXTAL input frequency. If OSCE=0,
Freescale Semiconductor
Signal Description
shows a block diagram of the OSCLCP.
RESET
EXTAL and XTAL
Detector
Peak
EXTAL
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Figure 7-1. Block diagram of S12CPMU
Figure 7-2. OSCLCP Block Diagram
Gain Control
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
Rf
V
V
DDPLL
SSPLL
= 1.8 V
OSCCLK
XTAL
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