sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 147

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

3.5.2
The S12PMMC controls the address buses and the data buses that interface the bus masters (CPU12,
S12SBDM) with the rest of the system (master buses). In addition the MMC handles all CPU read data
bus swapping operations. All internal resources are connected to specific target buses (see
3.5.2.1
The arbitration scheme allows only one master to be connected to a target at any given time. The following
rules apply when prioritizing accesses from different masters to the same target bus:
3.5.3
The MMC does not generate any interrupts
Freescale Semiconductor
•
•
CPU12 always has priority over BDM.
BDM has priority over CPU12 when its access is stalled for more than 128 cycles. In the later case
the CPU will be stalled after finishing the current operation and the BDM will gain access to the
bus.
Chip Bus Control
Interrupts
Master Bus Prioritization regarding Access Conflicts on Target Buses
P-Flash
DBG
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
D-Flash
Figure 3-12. S12P platform
MMC “Crossbar Switch”
resources
CPU
BDM
XBUS0
S12X0
SRAM
S12P Memory Map Control (S12PMMCV1)
S12X1
Peripherals
BDM
IPBI
Figure
3-12).
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