sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 242

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
7.3.2.7
This register controls the PLL functionality.
Read: Anytime
Write: Anytime if PROT=0 (CPMUPROT register) and PLLSEL=1 (CPMUCLKS register). Else write has
no effect.
242
0x003A
FM1, FM0
Reset
Field
5, 4
W
R
PLL Frequency Modulation Enable Bits — FM1 and FM0 enable frequency modulation on the VCOCLK. This
is to reduce noise emission. The modulation frequency is f
S12CPMU PLL Control Register (CPMUPLL)
0
0
7
Write to this register clears the LOCK and UPOSC status bits.
Care should be taken to ensure that the bus frequency does not exceed the
specified maximum when frequency modulation is enabled.
The frequency modulation (FM1 and FM0) can not be used if the Oscillator
Filter is enabled.
Figure 7-10. S12CPMU PLL Control Register (CPMUPLL)
0
0
6
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 7-6. CPMUPLL Field Descriptions
Table 7-7. FM Amplitude selection
FM1
FM1
0
5
0
0
1
1
0
1
0
1
FM0
NOTE
NOTE
NOTE
FM0
0
4
Description
FM Amplitude /
FM off
f
1%
2%
4%
VCO
ref
0
0
3
divided by 16. See
Variation
0
0
2
Table 7-7
Freescale Semiconductor
0
0
1
for coding.
0
0
0