sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 229

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

7.1.2.3
This mode is entered by executing the CPU STOP instruction.
The voltage regulator is in Reduced Power Mode (RPM).
The API is available.
The Phase Locked Loop (PLL) is off.
The Internal Reference Clock (IRC1M) is off.
Core Clock, Bus Clock and BDM Clock are stopped.
Depending on the setting of the PSTP and the OSCE bit, Stop Mode can be differentiated between Full
Stop Mode (PSTP = 0 or OSCE=0) and Pseudo Stop Mode (PSTP = 1 and OSCE=1).
Freescale Semiconductor
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Full Stop Mode (PSTP=0 or OSCE=0)
The external oscillator (OSCLCP) is disabled.
After wake-up from Full Stop Mode the Core Clock and Bus Clock are running on PLLCLK
(PLLSEL=1). After wake-up from Full Stop Mode COP and RTI are running on IRCCLK
(COPOSCSEL=0, RTIOSCSEL=0).
Pseudo Stop Mode (PSTP=1 and OSCE=1)
The external oscillator (OSCLCP) continues torun. If the respective enable bits are set the COP and
RTI will continue to run.
The clock configuration bits PLLSEL, COPOSCSEL, RTIOSCSEL are unchanged.
Stop Mode
When starting up the external oscillator (either by programming OSCE bit
to 1 or on exit from Full Stop Mode with OSCE bit already 1) the software
must wait for a minimum time equivalent to the startup-time of the external
oscillator t
UPOSC
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
before entering Pseudo Stop Mode.
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
NOTE
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