sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 707

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

value, DUTY, contained in D[10:1] in MCDCx. When a match (output compare between motor controller
timer counter and DUTY) occurs, the PWM output will toggle to a logic high level and will remain at a
logic high level until the motor controller timer counter overflows (reaches the value defined by
P[10:1] – 1 in MCPER). After the motor controller timer counter resets to 0x000, the PWM output will
return to a logic low level. This completes the first half of the PWM period. During the second half of the
PWM period, the PWM output will remain at a logic low level until either the motor controller timer
counter matches the 10-bit PWM duty cycle value, DUTY, contained in D[10:1] in MCDCx if D0 = 0, or
the motor controller timer counter matches the 10-bit PWM duty cycle value + 1 (the value of D[10:1] in
MCDCx is increment by 1 and is compared with the motor controller timer counter value) if D0 = 1 in the
corresponding duty cycle register. When a match occurs, the PWM output will toggle to a logic high level
and will remain at a logic high level until the motor controller timer counter overflows (reaches the value
defined by P[10:1] – 1 in MCPER). After the motor controller timer counter resets to 0x000, the PWM
output will return to a logic low level.
This process will repeat every number of counts of the motor controller timer counter defined by the period
register contents (P[10:0]). If the output is neither set to 0% nor to 100% there will be four edges on the
PWM output per PWM period in this case. Therefore, the PWM output compare function will alternate
between DUTY and DUTY + 1 every half PWM period if D0 in the corresponding duty cycle register is
set to 1. The relationship between the motor controller timer counter clock (f
counter value, and left aligned PWM output if DITH = 1 is shown in
Figure 19-20
dither feature enabled and D0 = 1. Please note: In the following examples, the MCPER value is defined
by the bits P[10:0], which is, if DITH = 1, always an even number.
Freescale Semiconductor
Motor Controller
Motor Controller
Figure 19-18. PWM Output: DITH = 1, MCAM[1:0] = 01, MCDC = 31, MCPER = 200, RECIRC = 0
Timer Counter
Timer Counter
PWM Output
and
The DITH bit must be changed only if the motor controller is disabled (all
channels disabled or period register cleared) to avoid erroneous waveforms.
Clock
Figure 19-21
0
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
show right aligned and center aligned PWM operation respectively, with
15
100 Counts
16
NOTE
1 Period
99
0
15
100 Counts
Figure 19-18
TC
16
), motor controller timer
Motor Controller (MC10B8CV1)
and
99
Figure
0
19-19.
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