sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 237

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

7.3.2.3
The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK.
Read: Anytime
Write: If PLLSEL=1 write anytime, else write has no effect.
7.3.2.4
This register provides S12CPMU status bits and flags.
Read: Anytime
Freescale Semiconductor
1. PORF is set to 1 when a power on reset occurs. Unaffected by System Reset.
2. LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset.
3. ILAF is set to 1 when an illegal address reset occurs. Unaffected by System Reset. Cleared by power on reset.
0x0036
0x0037
Reset
Reset
If PLL is selected (PLLSEL=1)
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
W
W
R
R
RTIF
S12CPMU Post Divider Register (CPMUPOSTDIV)
S12CPMU Flags Register (CPMUFLG)
0
0
0
7
7
= Unimplemented or Reserved
= Unimplemented or Reserved
Figure 7-6. S12CPMU Post Divider Register (CPMUPOSTDIV)
Note 1
PORF
0
0
6
6
Figure 7-7. S12CPMU Flags Register (CPMUFLG)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
f PLL
f PLL
f bus
Note 2
LVRF
0
0
5
5
=
=
=
f PLL
------------- -
---------------------------------------- -
f VCO
--------------- -
POSTDIV
2
4
S12 Clock, Reset and Power Management Unit (S12CPMU) Block Description
f VCO
LOCKIF
0
0
4
4
+
1
LOCK
0
0
3
3
POSTDIV[4:0]
Note 3
ILAF
0
2
2
OSCIF
1
0
1
1
UPOSC
1
0
0
0
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