sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 691

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

19.3.2
19.3.2.1
This register controls the operating mode of the motor controller module.
Freescale Semiconductor
MCPRE[1:0]
MCSWAI
Offset Module Base + 0x0000
Reset
MCTOIF
FAST
Field
DITH
6:5
4
3
2
0
W
R
1
Write accesses to “Reserved” addresses have no effect. Read accesses to “Reserved” addresses provide
invalid data (0x0000).
0x003E
0x003F
Offset
Register Descriptions
Motor Controller Module Stop in Wait Mode
0 Entering wait mode has no effect on the motor controller module and the associated port pins maintain the
1 Entering wait mode will stop the clock of the module and debias the analog circuitry. The
0 PWM operates in 11-bit resolution mode, duty cycle registers of all channels are switched to word mode.
1 PWM operates in 7-bit resolution (fast) mode, duty cycle registers of all channels are switched to byte mode.
0 Dither feature is disabled.
1 Dither feature is enabled.
0 A motor controller timer counter overflow has not occurred since the last reset or since the bit was cleared.
1 A motor controller timer counter overflow has occurred.
Motor Controller Prescaler Select — MCPRE1 and MCPRE0 determine the prescaler value that sets the
Motor Controller PWM Resolution Mode
Motor Control/Driver Dither Feature Enable (refer to
Motor Controller Timer Counter Overflow Interrupt Flag — This bit is set when a motor controller timer
Motor Controller Control Register 0
7
0
0
functionality they had prior to entering wait mode both during wait mode and after exiting wait mode.
motor controller timer counter clock frequency (f
clock (f
frequency f
the possible combinations of MCPRE1 and MCPRE0
module will release the pins.
counter overflow occurs. The bit is cleared by writing a 1 to the bit.
Reserved
Reserved
= Unimplemented or Reserved
BUS
Figure 19-3. Motor Controller Control Register 0 (MCCTL0)
) as shown in
TC
6
0
until the start of the next PWM period.
MCPRE[1:0]
Figure 19-2. MC10B8C Memory Map (continued)
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
Table 19-3. MCCTL0 Field Descriptions
Figure
5
0
19-22. Writes to MCPRE1 or MCPRE0 will not affect the timer counter clock
MCSWAI
Register
4
0
Description
TC
). The clock source for the prescaler is the peripheral bus
Table 19-4
Section 19.4.1.3.5, “Dither Bit
FAST
3
0
shows the prescaler values that result from
DITH
2
0
Motor Controller (MC10B8CV1)
(DITH)”)
1
0
0
Access
—
—
MCTOIF
0
0
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