sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 345

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

software simpler because only one address area is applicable for the transmit process, and the required
address space is minimized.
The CPU then stores the identifier, the control bits, and the data content into one of the transmit buffers.
Finally, the buffer is flagged as ready for transmission by clearing the associated TXE flag.
The MSCAN then schedules the message for transmission and signals the successful transmission of the
buffer by setting the associated TXE flag. A transmit interrupt (see
is generated
If more than one buffer is scheduled for transmission when the CAN bus becomes available for arbitration,
the MSCAN uses the local priority setting of the three buffers to determine the prioritization. For this
purpose, every transmit buffer has an 8-bit local priority field (PRIO). The application software programs
this field when the message is set up. The local priority reflects the priority of this particular message
relative to the set of messages being transmitted from this node. The lowest binary value of the PRIO field
is defined to be the highest priority. The internal scheduling process takes place whenever the MSCAN
arbitrates for the CAN bus. This is also the case after the occurrence of a transmission error.
When a high priority message is scheduled by the application software, it may become necessary to abort
a lower priority message in one of the three transmit buffers. Because messages that are already in
transmission cannot be aborted, the user must request the abort by setting the corresponding abort request
bit (ABTRQ) (see
(CANTARQ)”.) The MSCAN then grants the request, if possible, by:
9.4.2.3
The received messages are stored in a five stage input FIFO. The five message buffers are alternately
mapped into a single memory area (see
associated with the MSCAN, but the foreground receive buffer (RxFG) is addressable by the CPU (see
Figure
the receive process.
All receive buffers have a size of 15 bytes to store the CAN control bits, the identifier (standard or
extended), the data contents, and a time stamp, if enabled (see
Message
The receiver full flag (RXF) (see
the status of the foreground receive buffer. When the buffer contains a correctly received message with a
matching identifier, this flag is set.
On reception, each message is checked to see whether it passes the filter (see
Acceptance
valid message, the MSCAN shifts the content of RxBG into the receiver FIFO
1. The transmit interrupt occurs only if not masked. A polling scheme can be applied on TXEx also.
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1. Setting the corresponding abort acknowledge flag (ABTAK) in the CANTAAK register.
2. Setting the associated TXE flag to release the buffer.
3. Generating a transmit interrupt. The transmit interrupt handler software can determine from the
9-39). This scheme simplifies the handler software because only one address area is applicable for
setting of the ABTAK flag whether the message was aborted (ABTAK = 1) or sent (ABTAK = 0).
Storage”).
1
Filter”) and simultaneously is written into the active RxBG. After successful reception of a
Receive Structures
when TXEx is set and can be used to drive the application software to re-load the buffer.
Section 9.3.2.9, “MSCAN Transmitter Message Abort Request Register
MC9S12HY/HA-Family Reference Manual Rev. 1.04
Section 9.3.2.5, “MSCAN Receiver Flag Register
Figure
9-39). The background receive buffer (RxBG) is exclusively
Freescale’s Scalable Controller Area Network (S12MSCANV3)
Section 9.3.3, “Programmer’s Model of
Section 9.4.7.2, “Transmit
Section 9.4.3, “Identifier
2
, sets the RXF flag, and
(CANRFLG)”) signals
Interrupt”)
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