sc9s12hy64j0vllr Freescale Semiconductor, Inc, sc9s12hy64j0vllr Datasheet - Page 132

• Manufacturer Part Number: sc9s12hy64j0vllr
• Description: S12 Microcontrollers Mcu 16-bit Hcs12 Cisc 32kb Flash 5v Tray
• Manufacturer: Freescale Semiconductor, Inc

Port Integration Module (S12HYPIMV1)
A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4
consecutive samples of an active level directly or indirectly.
The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock
is generated by an RC-oscillator in the Port Integration Module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin individually:
Sample count <= 4 and interrupt enabled (PIE=1) and interrupt flag not set (PIF=0).
132
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
1
These values include the spread of the oscillator frequency over tempera-
Uncertain
ture, voltage and process.
Figure 2-88. Interrupt Glitch Filter on Port P and J (PPS=0)
Ignored
Pulse
Valid
MC9S12HY/HA-Family Reference Manual, Rev. 1.04
t
Table 2-75. Pulse Detection Criteria
pign
Figure 2-89. Pulse Illustration
t
pval
3 < t
t
t
pulse
pulse
pulse
STOP
uncertain
< 4
3
4
t
pulse
bus clocks
bus clocks
bus clocks
Unit
Mode
t
pign
STOP
< t
t
t
pulse
pulse
pulse
1
< t
t
t
pign
pval
pval
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